This invention relates generally to data communication systems and, more particularly, to a data network system and method wherein a controller that receives and stores data in its internal memory buffer can automatically invoke a Direct Memory Access (DMA) mode of data transfer to prevent overflowed data from being lost.
The task of accommodating increasing bus traffic in data communication networks continues to pose as a challenge. The primary bottle-neck in most data communication networks appears to be the system bus. The system bus is a bottle-neck primarily because many devices share the same bus and must contend for its use in transmitting or receiving data. For this reason, the system bus may be unavailable at crucial times for reasons such as operating priorities, system interrupts, and other bus traffic. Thus, in a computer system, it is necessary to buffer data received to accommodate bus traffic with other data devices.
Examples of devices buffering data received to accommodate bus traffic with other data sources and sinks include data conversion devices. Data conversion devices are basically front end communications processors that act as the interface between the host CPU and external terminals. Data conversions devices provide limited internal storage to continue receiving data from data sources while waiting for converted data to be moved to data sinks via the system bus.
Since the prior art solution is to provide storage capability while the system bus is busy, there exists an inherent problem in the prior art solution. This problem manifests when the period during which the system bus remains busy is long enough so that the amount of data accumulated in the temporary storage exceeds its storing capacity. When that occurs, data may be lost. To prevent data loss, data must be transferred to another location.
Generally, the data transport techniques most commonly used are Programmed I/O and Direct Memory Access (DMA). With Programmed I/O, the Host CPU is involved in every aspect of the data transport process. Even if the network adapter""s control and data port parameters are defined and mapped in system memory, the performance of the network/system interface is, in most cases, limited by the CPU""s input/output bandwidth and system bus utilization. Moreover, because Programmed I/O utilizes the CPU in every aspect of transferring data, when used as the transport mechanism in preventing data loss due to other bus traffic, this technique or those using the Host CPU as the main driving force in the data transport process is subject to an additional possibility of data loss when CPU interrupt latency rises due to CPU workload.
Direct Memory Access (DMA), on the other hand, is designed to transfer large xe2x80x9cblocks or units of dataxe2x80x9d with little or no Host CPU intervention. Most DMA transport mechanisms are based on the Master-Slave transport model. With this type of transport mechanism, the Host CPU initiates the data move or transfer, and once started, the Host CPU is not involved again until the entire xe2x80x9cblock or unit of dataxe2x80x9d has been transferred. For this reason, DMA is much more efficient in term of CPU time required and is a preferred method to transfer large blocks of data than Programmed I/O or other CPU-intensive data transfer methods on the whole. On the other hand, DMA data transfer is slower than Programmed I/O and other CPU-intensive data transfer methods due to the extra moving steps involved in DMA transfer. Moreover, DMA techniques, such as DMA masters and DMA slaves, have their limitation in that additional processing is normally required to move data from where the DMA process puts it to the data sink (e.g., a specified application memory location). This is because the DMA controller is not able to determine the type and size of data, and the CPU must examine the data to determine the proper data sink.
For the above reasons, in devising a data transport technique to use in moving data from the temporary storage buffer to another location, a dual approach, which utilizes non-DMA data transfer (e.g., Programmed I/O) to move data to the proper sink in most instances but switches to DMA transfer if the internal storage limit is approached, is most desirable. Current commercially available data conversion devices that are DMA masters (e.g., Cirrus Logic CD-2400 Serial Interface Controller) or DMA slaves (e.g., Advanced Micro Devices Am7990 Lance Ethernet Controller) do not allow the CPU to move data from internal storage. On the other hand, commercially available data conversion devices with internal storage that rely on the CPU to move data (e.g., National Semiconductor 16550 AFN Serial Interface Controller) have the aforementioned additional possibility of data loss when CPU latency rises due to its workload.
Thus, it is desirable to provide the capability for automatic switching between a non-DMA data transfer mode and a DMA transfer mode to move data from the buffer storage to another location before the buffer storage is full.
Furthermore, it is desirable to provide an internal storage manager to monitor the fill and drain streams of data frames together with the current buffer capacity for storage to decide whether data loss is anticipated before switching to a DMA data transfer mode.
Accordingly, one advantage of the invention is in providing a network controller that has the ability to accumulate data received in its internal buffer storage and to selectively engage between a non-DMA data transfer mode and a DMA transfer mode to transfer data from the internal buffer storage to another location before it is full.
Another advantage of the invention is in providing an internal storage manager that monitors the fill and drain streams of data frames together with the current buffer storage capacity of a network controller to determine whether data loss is anticipated before switching to a DMA data transfer mode.
The above and other advantages of the invention are achieved, at least, in part, by providing a system for receiving from a plurality of terminals data frames to be processed by a host processor that comprises a controller responsive to the data frames for providing an interface between the terminals and the host processor and having a memory buffer for holding the data frames received from the terminals for processing by the host processor. Also, a system memory having a capacity larger than the memory buffer is available for storing the data frames received from the plurality of terminals. While a non-DMA data transfer mode is normally used to transfer data from the memory buffer to any desired location, a DMA means responsive to the host processor is used for writing the data frames received from the terminals into the system memory. The controller includes a buffer manager for monitoring the data frames supplied to the memory buffer and switching means responsive to the buffer manager for automatically engaging the DMA means. While the controller is preferably provided on a chip external with respect to the system memory, the DMA means may be provided either on the chip or externally.
In accordance with one feature of the invention, the DMA means is engaged to transfer data frames received from the terminals to the system memory when the number of data frames received from the terminals exceeds a predetermined number.
In accordance with another feature of the invention, the DMA means is engaged to transfer data frames received from the terminals to the system memory when the time period during which the frames have been received from the terminals exceeds a predetermined period.
In accordance with a further feature of the invention, the DMA means is engaged to transfer data frames received from the terminals to the system memory when the capacity of the memory buffer occupied by the data frames exceeds a predetermined value.
Preferably, the buffer manager makes a decision whether to engage the DMA means based on the rate of loading data frames into the memory buffer and the rate of unloading data frames from the memory buffer. The switching means disengages the DMA means in response to an instruction from the host processor.
In accordance with a further aspect of the invention, the buffer manager arbitrates the priority between requests for access to load data frames into the memory buffer and requests for access to unload data frames from the memory buffer. Preferably, the loading requests have higher priority than the unloading requests.
In accordance with another aspect of the invention, in a network controller for receiving data frames having an internal memory buffer for holding the data frames received from a network for processing by a host processor, a DMA means for transferring the received data frames into a system memory, a buffer manager, and a decision logic means. The buffer manager comprises a held frame monitor which is responsive to the memory buffer and is used in monitoring data frames that are loaded into as well as unloaded from the memory buffer. The decision logic means is responsive to the buffer manager and is used to automatically engage the DMA means in unloading data frames from memory buffer when its overflow is anticipated.
In a preferred embodiment of the invention, the buffer manager further comprises a loading means responsive to the data frames received for generating word storage addresses to write the data frames into the memory buffer. The buffer manager further comprises an unloading means responsive to the memory buffer for generating addresses for DMA unloading of data frames. In response to the host processor, a host address means generates addresses that are used by the host processor to read the data frames from the memory buffer. A memory arbitration means which is responsive to signals associated with the data frames received, the unloading means, and the host processor to determine whether to write the data frames into the memory buffer or to read the data frames from the memory buffer. A memory address multiplexer selectively provides the memory buffer with the addresses generated by the loading means, unloading means, and host address means in response to a control signal from the memory arbitration means.
In accordance with one preferred embodiment, the held frame monitor comprises a held frame counter. The count value in the held frame counter reflects the number of frames loaded into the memory buffer minus the number of frames unloaded from the memory buffer. The decision logic means compares the count value supplied by the held frame counter with a variable threshold value to engage the DMA means in unloading the memory buffer when the count value exceeds the threshold value. As an example, the threshold value may be based on the rate of unloading said data frames from the memory buffer.
In accordance with another preferred embodiment of the invention, the held frame monitor comprises a timer means to measure the time interval during which the data frames are loaded into the memory buffer. When the time interval supplied by the timer exceeds a predetermined value, the decision logic means engages the DMA means in unloading the data frames from the memory buffer. The predetermined value may be based on the rate of unloading data frames from the memory buffer. The timer means is reset when all frames are unloaded from the memory buffer.
In accordance with one feature of the invention, the DMA means unloads a part of a data frame which is still being loaded into the memory buffer.
In accordance with another feature, the DMA means unloads a data frame only after the frame is completely loaded into the memory buffer. In this case, the status and length fields are added to the beginning of the frame.
The DMA means may comprise a DMA access logic that is a part of the network controller and a DMA controller that is external to the network controller. The internal memory buffer may also be provided on the controller chip. The system memory may be provided externally with respect to the chip.
In accordance with a method of the present invention, the following steps are carried out:
loading the received data frames into a buffer of the network controller,
supplying the host processor with the frames unloaded from the buffer,
monitoring the frames loaded into the buffer and unloaded from the buffer, and
automatically switching into a DMA transfer mode to use a DMA controller for moving data into a system memory, when overflow of the buffer is anticipated.
Overflow of the buffer may be anticipated based on the number of data frames accumulated in the buffer and based on the rates of loading the frames into the buffer and unloading the frames from the buffer. Overflow of the buffer may also be based on the remaining capacity of the buffer to hold new frames coupled with the rate of unloading the frames from the buffer. Finally, overflow anticipation may be based on a time period during which data frames are loaded into the memory buffer and the rate of unloading the frames from the memory buffer.
Still other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.